1. Field of the Invention
This invention relates to high density integrated circuit (IC) structures, and more particularly to a multilayer 3-D assembly employing a collection of discrete IC chips.
2. Description of the Related Art
There is a continuing need for microelectronic systems employing high density circuits with many data lines. Such systems are conventionally constructed with prefabricated IC circuits sealed in packages, mounted on printed circuit boards and provided with interconnections between the circuit packages by means of connectors, backplanes and wiring harnesses. To reduce the size, weight and power consumption of such systems, multiple chips can be sealed inside a single package. This multiple packaging approach raises the level of integration at the lowest packaging level, and improves the system size, weight and power characteristics.
A much higher level of integration at this lowest packaging level has been achieved with a new 3-D microelectronics technology which reorganizes the physical structure and approach to parallel computing. The 3-D computer employs a large number of parallel processors, typically 10.sup.4 -10.sup.6, in a cellular array configuration. A wide variety of computationally intensive applications can be performed by this processor with substantial system level advantages. To handle the very large number of data lines (typically 10.sup.4 -10.sup.6), a stacked wafer approach is taken, with electrical signals passing through each wafer by means of specially processed feedthroughs. The wafers are interconnected by means of micro-bridges.
The 3-D computer is described in U.S. Pat. No. 4,507,726 to Grinberg et al. and U.S. Pat. No. 4,707,859 to Nudd et al., both assigned to Hughes Aircraft Company, the assignee of the present invention. As shown in FIG. 1, a plurality of elemental array processors are provided which are composed of a vertical stack of modules. The modules are arranged as functional planes, 2, 4 and 6. Modules of a similar functional type are located on each plane. For example, comparator modules 8 might be located on plane 12, and memory modules 10 on plane 4. Plane 6 typically contains modules 12 that are used to perform particular image processing functions. Additional planes may be added below the plane 6 as needed to complete the processing functions.
Each elemental processor is composed of a vertical stack of modules 8, 10 and 12. Each processor is designed to perform operations on a single data element. Signals are transferred between modules in each processor using data buses. For example, signals may be passed between a module 8 and a corresponding module 10 using a data bus 14. Similarly, signals are passed between a module 10 and a corresponding module 12 using a data bus 16.
The overall processor is intended to be employed for two-dimensional image analysis. To process an image, the image is converted into suitable binary form for use by the elemental processors by an array 18 of photosensors 20. The photosensors 20 are arranged in a matrix such that there is one photosensor 20 for each of the elemental processors. The number of photosensors 20 (and hence the number of processes) corresponds to the number of picture elements (pixels) into which an image 22 to be analyzed is to be divided. Each photosensor 20 provides a sensor output signal on a data bus 24 to a corresponding comparator module 8, where it appears as a comparator input signal. The magnitude of the sensor output signal is proportional to the brightness of the corresponding pixel of the image 22.
The various planes 2, 4, 6 are implemented as separate wafers, each wafer having a unitary IC distributed over its upper surface with monolithically integrated interconnections between circuit elements. Interconnections between adjacent wafers in the stack are formed by electrically conductive feedthroughs which extend through the wafers from the IC on the upper surface to the lower surface, and a collection of spring contacts on both the upper and lower sides of the wafers. The spring contacts on the upper sides of the wafers make electrical contact with selected locations on the IC, while the spring contacts on the bottom electrically connect to selected feedthroughs. The spring contacts are positioned so that the ones on top of a wafer bear against and electrically connect to corresponding spring contacts on the bottom of the next wafer above. The feedthroughs can be formed by a thermal migration of aluminum, while the spring contacts are implemented as micro-bridges. Both techniques are described in U.S. Pat. Nos. 4,239,312 and 4,275,410, assigned to Hughes Aircraft Company.
While the processor described above provides a very high density of circuitry, it is limited in the sense that a custom designed IC is fabricated on each wafer, and that wafer can serve no other purpose. Furthermore, each wafer is generally limited to a single class of circuitry CMOS, bipolar, I.sup.2 L, etc.). A different approach to high density circuit packaging which provides a greater degree of freedom in the flexibility of circuit design is disclosed in a paper by R. O. Carlson et al., "A High Density Copper/Polyimide Overlay Interconnection", Eighth International Electronics Packaging Conference, Nov. 7-10, 1988. With this approach, discrete pre-fabricated "off-the-shelf" IC chips can be integrated and interconnected into a single layer. Changes in circuit design can be accommodated by merely changing the discrete chips, with an accompanying change in the interconnections as necessary. The separate chips are set in openings cut through an alumina or silicon frame, and bonded in place with a thermoplastic resin such as duPont "Pyralin". The frame thickness is chosen to be a little less than most silicon chips, typically 20 mils. The frame is bonded to an alumina or silicon substrate, about 50 mils thick, which provides heat dissipation. The chips can be placed very close together; 5-10 mils are said to be typical chip spacings and spacings to the recess walls.
A polyimide sheet is then laminated over the frame. A computer-controlled laser beam is next used to open vias through the polyimide sheet down to selected locations on the chips. Interconnect metallization between the chips is formed by sputtering over the entire surface a thin adhesive metal followed by a thin copper sputtering, a thick copper plating, and a final adhesive metal sputtering. The metals are patterned into the interconnecting network by exposing a negative resist with the computer controlled laser beam, and removing undesired metal with etches. The metallization extends down through the vias to contact the selected locations on the chips. Successive signal layers are built up by spraying or spinning on a polyimide dielectric, opening vias with the laser to the underlying metal layer, and depositing metals and patterning with a photo-resist/etching process.
While the described approach provides a high packing density of bare chips, it is limited to a two-dimensional array and is not applicable to a three-dimensional stack. The use of a conductive heat dissipating substrate in fact prevents the use of the underside of the device for carrying electrically separated interconnects to another level below. The construction of the assembly also makes it difficult to efficiently test either the interconnect metallization (the "routing") or individual chips. If the routing is tested and found to be defective, the assembly will either be discarded or the routing repaired. If the assembly is discarded, the chips that have already been put in place prior to formation of the routing will be lost. If the routing is repaired by stripping it away and doing it over again, there is a risk of damaging the underlying chips. If, on the other hand, the routing is found to be correct but a chip found to be defective once the assembly has been completed, it is necessary to strip off the overlying routing to access and replace the defective chip, and then reform the entire routing network.